7CHIP: THE 8085 MACHINE CYCLES AND BUS TIMING and memory read

The 8085 micro-processor is designed to execute 74 different instruction types. Each instruction has two parts: operation code, an operand. The op-code is a command such as add and the operand is the object to be operated on, such as a byte or the content of register. Some instruction is 1-bytes instruction and some are multi bytes instruction

To execute instruction, the 8085 needs to perform various operations such as memory read/write and I/O read/write. However there is no direct relationship between the number of the bytes of an instruction and the number of the operation s 8085 signals and to perform.

Basically the micro-processor have three major function

These function are further divided to various operation

The first operation in any instruction is op-code fetch. The micro-processor needs to get this machine code from the memory register where it is stored before the micro-processor can begin execute the instruction

This op-code fetch cycle is called M1 cycle and has four t-state . this 8085 uses the first three states T1-T3 to fetch the code and T4 to decode and execute the op-code .in the 8085 the instruction set some instruction have six T-state .

timing diagram of op-code fetch

MEMORY READ MACHINE CYCLE

to illustrate the memory read machine cycle , we need to examine the execution of a 2 bytes or 3 byte instruction because in a 1 byte instruction the machine code is an op code;therefor the operation is always op code fetch.the execution of a 2 bytes instruction is illustrated in example.

question?:the machine codes 0011 1110 (3EH) and 0011 0010 (32H) are stored in memory locations 2000H , respectively , as shown below.the first machine code 3 EH represent the op code to load a data byte in the accumulator . and the second code 32H represent the data bytes to be loaded in the accumulator .illustrate the bus timing as these machine codes are executed . calculated the timer required to execute . calculated the time require to execute the op code fetch and the memory read cycle and the entire instruction cycle if the clock frequency is 2MHz.

this instruction have two steps. first step is op code fetch second is data fetch. first step take 4 cycle and second take 3 cycle.second cycle is memory read cycle .

1. the first machine cycle M1 ( op code fetch) is identical in bus timing with the machine cycle .

at t1 micro processor identifies that it is an op code fetch cycle by placing 011 on the status signals ( IO/M bar=0,s1=1,s0=1) it places the memory address 2000H from the program counter on the address bus.20H on a15-a8.and 00H on AD7-AD0 and increments the program counter to 2001H to point to the next machine code.The ALE signal goes high during T1 which is used to latch the low-order address 00H from the bus AD7-AD0 . at T2 ,the 8085 asserts the RD bar control signal, which enables the memory , and the memory places the byte 3EH from location 2000H on the data bus . Then the 8085 places the op code in the instruction register and disable the RD bar signal. The fetch cycle is completed in state T3 .during T4 the 8085 decodes the op code and finds out that the second bytes needs to read . after the T3 state the the contents of the bus A15-A8 are unknown . and the data bus AD7-AD0 goes into high impedance.

2.After completion of the op code fetch cycle the 8085 places the address 2001H on the address bus and increments the program counter to the next address 2002H . the second machine cycle M2 is identified as the Memory read cycle (IO/M bar=0, S1=1 and S2=0) and the ALE is asserted at T2 the RD bar signal become active and enable the memory chip.

3 . at the rising edge of T2 the 8085 activates the data bus as as input bus, memory places the data bytes 32H on the data bus and the 8085 reads and stores the byte in the accumulator during T3.