PIN DIAGRAM ATMEL 89C51
VCC:supply voltage
GND:ground(o v)
PORT O:
port 0 is a 8 bit open drain bi-directional I/O port.As an out port it can sink 8 TTL inputs.when 1's is written to port 0 pins it act as high impedance input.
to act as input pin:we should write logic one to the latch
when port 0 used as an output .writing a zero to the port SFR turns ON the lower FET and make the pin suitable for output operation. writing a ZERO to the pin turn on the lower pin and connect the port pin to logic ground
when a port latches are written a logic "1" . Q compliment of latches is "0".lower fet is off and PORT pin connected to VCC.
writing a '1' to the PORT 0 SFR make it suitable for input operations.PORT 0 need external pull up resistors to VCC.this pull up resistor limit the current drawn from VCC. MULTIPLEXER is used to select whether the PORT 0 is used for input /output port or lower order address data
bus.
//PROGRAMMING example
following code will continuously send out to PORT 0 the alternating value of 55H and AAH
;Toggle all bits of p0
BACK: MOV A,#55
MOV P0,A
ACALL DELAY
MOV A, #0AAH
MOV P0,A
ACALL DELAY
SJMP BACK
it must be noted that complementing 55H(01010101) turns it into AAH(10101010).By sending 55H and AAH to a given port continuously,we toggle all the bits of that port
PORT 0 as input
with resistors connected to port 0, in order to make it an input,the port must be programmed by writing 1 to all the bits.In the following code,port 0is configured first as an input portby writing 1's to it,an then data is received from that port and send to p1.
;Get a byte from p0 and send it to p1
MOV A,#OFFH ;A=FFH(value of A to FFH)
MOV P0,A ;make P0 an input port
;by writing all is to it
BACK: MOV A, P0 ;get data from P0
MOV P1,A ;send it to PORT 1
SJMP BACK ;keep doing it
DUAL ROLE OF PORT 0
It can be used as AD0-AD7 ADDRESS DATA BUS
PORT 1:
Port 1 is an 8 bit- bi-directional I/O port with internal pull up.the port 1 output buffers can sink/source four TTL inputs.when 1s is written to port 1 pins they are pulled high by the internal pull up and can be used as input . as input , port 1 pins that are externally being pulled low will source current because of the internal pull ups
port 1 also receives the low-order address bytes during flash programming and verification.
port1 connected to FET and also to vcc by a pull up resistor. when port SFR are written by logic zero at the D input latch output Q will be zero.and Q bar is 1 (Q compliment).this Q is connected to READ LATCH . Q compliment is connected to FET ,so FET will on.and PORT pin is grounded.
when PORT latch are written logic one.Q will "1" Q compliment "0".FET will off PORT pin are pulled up to VCC.
port 1 pin do not need external pull up resistor to VCC .writing "1" to PORT1 SFR pin turn on off the FET ,is connected to the PORT pin to VCC.through the internal pull up resistor thus putting in a logic high
writing a "1" to the PORT "1" SFR make the pin suitable for input operation
Reading the PORT SFR after writing a "1" to the SFR pin initiate an input operation writing a "0" to the PORT "1" SFR pin turn's on the FET and connect PORT pin to logic ground writing a "0" make the bit suitable for output operation
PORT 1 PIN DO NOT HAVE ANY DUAL FUNCTION
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PORT 2
port 2 is an 8-bit-bi-directional I/O port with internal pullups. the port 2 output buffers can sink/source four TTL inputs.when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs.As inputs port 2 pins that are externally being pulled low will sorce current because of the internal pullups.
port2 emit the high-order address bytes during accesses to external data memory and during accesses to external data memory that use 16-bit address (MOVX @ DPTR) ,in this application ,it uses storing internal pullups when emitting 1s.During access to external data memory that that uses 8-bit address (MOVX@R1) ,port 2 emit the content of the p2 special function register.
port 2 also receive the high-order address bit and some control signals during flash programming and verification
when 0 write- it act as a output pin
when 1 is write -it act as input pin
port2 pin connected to one FET and also connected to VCC through the pullup resistors.multiplexer connected to the port2 is use this port 2 as a input/output operation or address bus functions.port2 pin do not need external pull up resistors to VCC.writing a 1 to SFR pin turn off the FET.(Q is connected to a not gate) and connected the port pin to VCC through the pull up resistor.thus putting out a logic high and writing a 1 to the SFR pin makes it suitable
for input operation.
writing 0 to the SFR pin turns on the FET and make the pin suitable for output operation.
Reading the port SFR after writing a 1 initiate an input operation port2 pin are used to carry higher order address information during external memory access.port 2 address information is valid at the rising edge of ALE signal.
programming port 2 as input
to make port 2 an input,it must programmed as such by writing 1 to all it's bit's.in the following code,port 2 is configured first as an input port by writing 1s ti it.then data is received from that port and is sent to P1 continuously.
;Get a byte from P2 and send to P1
MOV A,#0FFH ; content of A = to 0FFH(external memory location)
MOV P2,A ; make P2 an input port by
; writing all is to it
BACK: MOV A,P2 ;get data from P2
MOV P1 ,A ; send it to PORT 1
SJMP BACK ;keep doing that
PORT 3
PORT 3 is an 8-bit bidirectional I/O port with internal pullups.The port 3 output buffers can sink/source four TTL inputs.when 1s are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs .as inputs port 3 pins that are externally being pulled low will source current because of the pullups.
port 3 also serves the function of various special features of the AT89C51
PORT 3 ALSO RECEIVE SOME CONTROL SIGNALS FOR FLASH PROGRAMMING AND VERIFICATIONS
port 3 pins are connected to 1 FET and also to the VCC through the pullups resistor when the port SFR are written in a logic "0" at D inputs the latch output Q become "0" and NAND gate is "1" output of the NAND gate is one irrespective of the alternative function select.
this turn on the FET and output the pin level to logic ground.writing a "0" to the port 3 SFR pin when it is configured as the input output pin make the pin suitable for output operation . writing a "1" to the port SFR pin turn off the FET and make the pin suitable for input operation
PORT 3 pin does not need any external pullups resistor and PORT 3 need to be selected for alternative function to be used for input /output operation
as can be seen in the picture ,port 3 consist of latch , an input buffer and an output driver.The latch is actually the same as the P3 SFR. if a one is written to the latch(P3.X),the pin becomes high impedance.Traditional 89C51 documentation say s this pin is configured as inputs.However ,this pin is also outputting the high level data stored in the same latch bit!if a probe is placed on the respective pin the high level voltage will be seen.Thus data has been written at the same time the direction has been specified
when the pin is configured as inputs a signal at the pin can be sampled by a reading instruction.The instruction is actually reading the pin through the inputs buffer and not the latch.Usually when reading the pin,the lecture is stored in the register or memory location specified by the instruction . So if the pin is read again , data is subjected to have change.
there are some instruction that do read the information in the latch. these instruction are called READ-MODIFY-WRITE(RMW). they are in charge of retrieving the data in the latch, modifying it to whatever the operands specify and then placing the results in the same latch . A good example of such instruction is the op code SETB.SETB P3.0 will retrieve the bit P3.0 (READ),set it(MODIFY) and then store the one (WRITE) in the corresponding latch bit (P3.0).ANL,ORL,XRL,JBC,CPL,INC,DEC,DJNZ,MOV bit C, and CLR are the other RMW instruction
to configured the port as an output,write a zero to the latch.the latch is now driving the output LO.Notice that the pin can not be read now through the input buffer as any signal entering the pin will have the same potential as ground .Remember that to output a high level,writing a one to the latch does the job although the pin is said to be configured as input.
PORT 3 is considered to be a quasi bi-directional port because when configured as input the pin does not float . to prove this ,refer to the image.If the latch has a one , the output driver is disabled. However , the pin , thanks to the internal pull up resistance,will source current if the pin is externally pulled low.For a load with very low impedance,the read may be affected by the fact that the internal pull up resistor has the largest voltage drop
Labels: ATMEL 89C51
