PENTIUM II AND PENTIUM III
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PENTIUM processor introduced the vector ( SIMD)instruction .These instructions are called streaming SIMD extension (SSE) instructions are used to efficiently process vector operations on floating point data.Four 32 bit floating point operand are packed in each of eight new 128 bit registers,called the XMM registers.The catche are similar to those in Pentium 2 ,with one major additional option.A version of the Pentium 3 processor have a 256 K byte L2 cache on the same chip as the processor,providing a higher bandwidth path to the L1 caches.
When they are were introduced in 1993,1995,1997 and 1999,the Pentium ,Pentium pro, Pentium 2,Pentium 3 processors had clock rate of 60,200,266 and 500 MHz respectively .Improvements in circuit technology and VLSI fabrication technique,which have allowed smaller transistor size and lower gate delays,have led to clock rates of up to 1 GHz for the current version of the PENTIUM 3 processor.Pentium processor are old ,now a days we didn't use it.
PENTIUM 4
Introduced in 2000 ,the initial version of the processor of the Pentium have clock rates from 1.3 to 1.5 GHz.The full IA -32 instruction set is supported,including the MMX and SSE instructions .the SSE instructions have been extended ( SSE2) to handle two packed 64 bit floating -point numbers or two packed 64 bit integers in the 128 bit XMM registers.The longer inters are useful in implanting the encryption and decryption operations need in secure data applications.Deeper pipelines-up to 20 stages compared to 10 in the Pentium 3 with shorter stages are one of the factors leading to the higher clock rates,along with improved circuit and fabrication technologies.
There are separate L1 data and instruction caches.The data caches has a capacity of 8 K bytes and uses 4 way set associative access to 64 byte caches blocks.the instruction caches is organized to hold decoded instruction execution path segments called traces.which can extend over more than one branch in the original program.If these paths are repeated,execution is faster.Of course ,checks must be made to verify that the same branches are taken when traces are repeated.The term traces caches is used to describe this caching strategy.The decoded instruction are represented as micro operations.Up to four micro operations are needed to represent an IA 32 instruction .The trace cache can hold a number of execution path segments consisting of a total of 12 K micro operations
The 256 K byte on chip L2 cache is organized into 128 byte blocks and is 8 way set associative.The transfer path between the L2 and L1 cache levels supports a transfer rate of 48 giga bytes/s compared to 16 gigabytes/s in the Pentium 3.
The system bus on the Pentium 4 provides a much higher transfer rate than that supported by the Pentium 3.The Pentium 4 system bus is 64 bits wide,and transfers can take place at 400MHz.The transfer rate is therefore 3.2 gigabytes/s as compared to 1 gigabyte/s in the Pentium 3.
.................................Labels: Intel Micro-Processors
