Instruction to the RALU are taken from the A Bus and stored temporally in the in the instruction register . The control unit decodes the instruction and generate the correct sequence of signal to have the RALU perform the desired function .
RALU BLOCK DIAGRAM
The 8096 performs most of the calculations in the RALU . The RALU contains:
1.A 17 bit ALU.
2.The Program Status Word (PSW).
3.The Program Counter.
4.A loop counter.
5.3– Temporary register.
All register are 16 bit or 17 bit wide.Some of the register have the ability to perform simple operations to off load the ALU . A separate incrementor is used for the PC;however ,jumps must be handled through the ALU.Two of the temporary register have their own shift logic.These register are used for the operation that require logical shift, including Normalize,Multiply and Divided.The 'Lower Word' Register is used only when double word quantities are being shifted , the 'Upper word' register is used whenever a shift is performed or as a temporary register for many instructions .Repetitive shift are counted by the 5 bit “Loop Counter”.
A Temporary register is used to store the second operand of two operand instructions.This include the multiplication and the divisor during the multiplication and divisions.In order to perform subtractions,the output of this register can be complimented before being placed into the “B” input of the ALU.
The DELAY section (RALU block diagram) is used to convert the 16 bit bus into 8 bit bus.This is required as all address and instruction are carried on the 8 bit A Bus.Server constants,such as 0,1, and 2 are stored in the RALU for use in speeding up certain calculations.These come in handy when the RALU needs to make a 2's compliment number or perform an increment or decrement instruction.
MEMORY:The addressable memory space on the 8096 consists of 64 KB , most of which are available to the user for program or data memory .Locations, which have special purpose ,are 0000H through 00FFH and 1FFFH through 2010H.All other locations can be used either for program or data storage or for memory mapped peripherals.
The Internal register location on the 8096 are divided into 2 groups.
1.A register File
2.A set of Special Function Register.
Location 00H through 0FFH contain Register File and Special Function Register(SFR's).No code can be executed from this internal RAM section .If an attempt to execute instruction from location 00H is made,the instruction will be fetched from external memory.This section is reserved for the development.Execution of the non-maskable interrupt will force a call to external location 0000H therefor ,the NMI and TRAP interrupt are also reserved for intel development tools.
RESERVED MEMORY:Locations 1FFEH and 1FFFH are reserved for Port 3 and Port 4 respectively .Locations 2000H through 2011H stores 9 vector Interrupt.The 9th Vector is used by Intel for its system development.Location 2012H through 2077H are reserved for Intel factory test.
The RALU can operate on any of the 256 internal register locations.Locations 00H through 17H are used to access the SFR's .Locations 18H and 19H contain the stack pointer .There are no restrictions on the use of the remaining 230 locations except that the code can be executed from them.
POWER DOWN:The upper 16 bit RAM locations receive their power from the Vpd pin.If it is desired to keep the memory in these location alive during a power down situation , all that is needed is to keep voltage on the Vpd pin.The current requirement to keep the RAM alive is approximately 1 mA.For normal situation power on both Vcc and Vpd must be applied.If power on Vpd is not applied , the RAM will function properly even if Vcc is appied.
TIMERS:Two 16 bit timers are available for use on the 8096.The 1st is designed 'Timer 1 , the 2nd 'Timer 2'.Timer 1 is used to synchronize events to real time,while timer 2 can be clocked externally and synchronize events occurrences.
Both Timer 1 and Timer 2 can be used to trigger a timer overflow interrupt and set a flag in the I/O Status Register 1 .The interrupt are controlled by IOCI.2 and IOCI,3 respectively.The flag are set in IOCI .6 and IOCI .7 respectively.
HIGH SPEED INPUTS:The high speed input unit can be used to record the time at which an events occurs w.r.t timer 1.There are 4 lines which can be used in this mode and up to a total of 8 evets can be recorded .HSI .2 and HSI .3 share pin with HSO.4 and HSO .5.The I/O control register are used to determined the functions of these pins.
HIGH SPEED OUTPUTS:the high speed output unit is used to trigger events at specific times with minimal CPU overhead.These events include , starting an ADC,resetting timer 2 setting 4 software flags,generating interrupts , and switching up to 6 output lines.Up to 8 evets can be pending at any time.
ANALOG INPUT:The ADC on the 8096 provides a 10 bit result on one of 8 input channels.Conversions is done using succesive approximation with a result equal to the ration of the input volatge divided by the analog supply voltage.If the ration is 1.0 then the result will be all ones.The ADC is available on the 8096,8397,9095 and 8395 members of the MCS 96 family .The input voltage must be in the range of 0 to Vref,the analog voltage and suppy voltage .For prper operation ,Vref must be held norminally at 5V.The ADC result is calculated from the formula.
1o24((input voltage-ANALOG)/(Vref-ANALOG)).
SERIAL PORT:The serial port is compatible with the MCDS-51 serial port .It is full duplex,meaning it can transmit and receive simultaneously .It is also receive buffered,meaning it can commence reception of a second byte before a previously received byte has been read from the receive register.The serial port register are both accessed at location 07H .A write to this location accesses the transmit register and a read accesses at location 07H.A write to this location accesses the transmit register and a read accesses a physically separate receive register .The serial port register are both accessed at location 07H .A write to this location accesses the transmit register and a read accesses a physically separate receive register.
The serial port operate in 4 modes.selection of these modes is done through the serial port control register at location 11H.
I/O PORT 0,1,2,3,and 4:The 8096 has five 8 bit I/O ports.Some of these ports are input only ,some output only some bidirectional and some have alternate functions.Input ports connect to the internal bus through an input buffer.Output ports connect through an output buffer to an internal register that holds the output buffer.Output ports connect through an output register that holds the output bits .Bi-directional ports consist of an internal register an output buffer and input buffer and an input buffer.
When an instruction accesses a bi-directional port as source register,the question often arises as to whether the value that is brought into the CPU comes from the internal port register or from the pins through input buffer,In the 8096 the value always comes from the port pins,never from the internal register.
WATCHDOG TIMER:This feature is provided as a means of graceful recovery from a software upset.If the software fails to reset the watchdog at least every 64K state times a hardware reset will be initiated.
The software can be designed so that the watchdog times out if the program does not progress properly.The watchdog will also times out if the software error was due to ESD (Electrostatic Discharge) or other hardware related problems.This prevents the controller from having a malfunctioning for longer than 16ms if a 12MHz oscillator is used.
Labels: MICRO CONTROLLER