The 8096A has following blocks
a,Serial Port
b,a Watchdog Timer
c,a Pulse – width Modulated output signals
The 8096 are available with and without ADC and and with and without on chip ROM .The 8097 is the ROMless version of 8096 with on-chip ADC.
The 8096 replace multiple chip solution by integrating a 16 bit CPU with all the I/O features and interface resource on a single piece of silicon represents highest level of integration in context with the micro controller.
It's internal circuit arrangements can be divided into several blocks for describing its operation as 1 and pinout in block diagram
ANGND:Reference power supply voltage for analog portion of the A/D converter.Nominally ANGND = +5V.
Vcc:Main supply voltage =+5V.
Vss:Digital circuit ground (0V).Pin 10 and 42 are meant for Vss and normally tied together.
Vpd:RAM standby power supply = +5.This voltage must be present during normal operation.
Vbb:substrate voltage from the on-chip back-bias generator.This pin should be connected to the ANGND through a 0.01 micro Farad capacitor.The capacitor is not required if A/D converter is not used.
The Block diagram of the 8096 contains
1.a CPU
2.a Programmable high speed I/O unit
3.an ADC.
4.a Serial port.
5.a Pulse width modulated output for digital to analog conversion.
The 8096 single chip micro controller is designed use in sophisticated real-time demanding applications such as industrial control,instrumentation and intelligent computer peripherals.The wide base applications cut across all industry segments have already been enumerated in application of micro controllers.With 16 bit horsepower , high speed math processing and high speed I/O , the 8096 is ideal for complex motor control and axis control systems.
CPU:The major component of the CPU of 8096 has register file and the RALU .Communication with the outside word is done either through the special function registers or the memory controller.The RALU does not use an accumulator . It operate directly on the 256 B register space made up of the register file and SFRs.Efficient I/O operations are possible by directly controlling the I/O operations are possible by directly controlling the I/O through the SFRs.The main benefits of this structure are the ability to quickly change contents, the absence of accumulator bottleneck , and fast through put and I/O times.
BUSES:A control unit and two buses connect the Register File and RALU .fig 3 shows CPU with its major bus connections.The two buses are 'A Bus' that is 8 bit wide and the 'D Bus' that is 16 bit wide the D Bus transfer data only between the RALU and the register File or Special Function register(SFR) . The A b=Bus is used as the address bus for above transfer or as a multiplexed address/data bus connecting to the 'Memory Controller'.any accesses of either the internal ROM or external memory are done though the “Memory controller”.Within the memory controller is a slave program counter which keeps track of the PC in the CPU.By having most program fetches from memory referenced to the slave PC,the processor slaves time as address seldom have to be sent to the memory controller .If the address jumps sequence then the slave PC is loaded with a new value and processing continues.Data fetches from memory are done through the memory controller , but the slave is bypassed for this operation.
REGISTER FILE:The Register File contains 232B of RAM that can be accessed as bytes , words,or double words.Since each of these location can be used by the RALU, there are essentially 232 'accumulators'.The first word in the Register File is reserved for use as the stack-pointer so it can not be used for data when stack manipulations taking place.Addressesfor accessing the Register File and SFRs are temporarily stored is two 8 bit address registers by the CPU hardware.
Labels: MICRO CONTROLLER